基于FPGA的PID算法学习———实现PI比例控制算法

前言

学习内容：参考网站：
PID算法控制
PID即：Proportional（比例）、Integral（积分）、Differential（微分）的缩写。也就是说，PID算法是结合这三种环节在一起的。
闭环控制：输出会影响到输入，进而逐渐逼近目标。

一、PI环控制算法

积分控制算法，就是为了消除稳态误差，由于积分是从0时刻一直积分到当前时刻 t，并且是对e(t)函数进行积分。
PI比例控制算法：
核心部分，大部分作用来自于P，I和D主要控制减小误差。
目标值：Target
实际值：Pid_out
误差值：e_t
上一时刻误差值：e_t
弥补值：u_t

相关公式：
误差值：e_t=Target - Pid_out
上一时刻误差值：e_t_1=e_t
弥补值：*u(t)=Kp ( e(t) - e(t-1)) + Ki * e(t)
输出值：Pid_out = Pid_out + u(t)

二、仿真分析验证

1.P环仿真

module PID_trol(input                     sys_clk  ,  input                     rst_n,   //signal  input		 signed	[7:0]  target,output reg signed	[7:0]  Pid_out);reg	signed	[15:0]		e_t;//目标值和现在值的差距reg	signed	[32:0]		u_t;//补偿值parameter signed K_p = 32'd300;parameter signed div = 8'd3;
//	 assign e_t = target - Pid_out;always @(posedge sys_clk or negedge rst_n)beginif(!rst_n)begine_t <= 16'd0;endelse begine_t <= target - Pid_out;endendalways @(posedge sys_clk or negedge rst_n)beginif(!rst_n)beginu_t <= 32'd0;endelse beginu_t <= (e_t * K_p )/1000;endendalways @(posedge sys_clk or negedge rst_n)beginif(!rst_n)beginPid_out <= 8'd0;endelse beginPid_out <= Pid_out + u_t;endendendmodule

2.PI环仿真

module PID_control(input                     sys_clk  ,  input                     rst_n,   //signal  input		 signed	[7:0]  target,output reg signed	[7:0]  Pid_out);reg	signed	[15:0]		e_t;//目标值和现在值的差距reg	signed	[15:0]		e_t_1;//上一时刻差距reg	signed	[32:0]		u_t;//补偿值parameter signed K_p = 32'd200;parameter signed div_p = 8'd3;parameter signed K_i = 32'd310;parameter signed div_i = 8'd3;
//	 assign e_t = target - Pid_out;always @(posedge sys_clk or negedge rst_n)beginif(!rst_n)begine_t <= 16'd0;endelse begine_t <= target - Pid_out;endendalways @(posedge sys_clk or negedge rst_n)beginif(!rst_n)begine_t_1 <= 16'd0;endelse begine_t_1 <= e_t;endendalways @(posedge sys_clk or negedge rst_n)beginif(!rst_n)beginu_t <= 32'd0;endelse beginu_t <= ((e_t - e_t_1) * K_p )/1000 + ( e_t * K_i)/1000 ;endendalways @(posedge sys_clk or negedge rst_n)beginif(!rst_n)beginPid_out <= 8'd0;endelse beginPid_out <= Pid_out + u_t;endendendmodule

3.顶层

`timescale 1ns / 1ps
//
// Company: 
// Engineer: 
// 
// Create Date: 2025/06/10 13:45:03
// Design Name: 
// Module Name: top
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//module top(input                     sys_clk  ,  input                     rst_n,   //signal  input		  signed	[7:0]  target,output wire signed	[7:0]  P_out,output wire signed	[7:0]  Pi_out);PID_control u_PI (.sys_clk   (sys_clk),.rst_n     (rst_n),.target    (target),.Pid_out   (Pi_out) );PID_trol u_P(.sys_clk   (sys_clk),.rst_n     (rst_n),.target    (target),.Pid_out   (P_out)
);
endmodule

4.测试文件

`timescale 1ns / 1ps
//
// Company: 
// Engineer: 
// 
// Create Date: 2025/06/10 13:48:03
// Design Name: 
// Module Name: tb_top
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//`timescale 1ns / 1psmodule tb_top();// 输入信号reg         sys_clk;reg         rst_n;reg signed [7:0] target;// 输出信号wire signed [7:0] P_out;wire signed [7:0] Pi_out;// 实例化顶层模块top u_top (.sys_clk (sys_clk),.rst_n   (rst_n),.target  (target),.P_out   (P_out),.Pi_out  (Pi_out));// 时钟生成（100MHz）initial beginsys_clk = 0;forever #10 sys_clk = ~sys_clk;  // 10ns周期 = 100MHzend// 测试激励initial begin// 初始化并复位rst_n = 0;target = 0;#20;  // 等待两个时钟周期// 释放复位rst_n = 1;#10;// 测试场景 1：正目标值target = 8'd100;   // +50endendmodule

5.仿真波形

总结

加上I之后，整体上升缓和了一点，同时调整速度缩短了一点。